JFETS fabricated on silicon substrates which employ boron and/or phosphorous in the constituent layers or regions are quite well known. For example, U.S. Pat. No. 4,322,738, issued to Bell, et al., describes a buried n-channel JFETS said to have very low gate leakage current and excellent noise and matching characteristics. According to Bell, et al., a p-type monocrystalline silicon substrate, or "slice," has a spin-on arsenic source applied to it, the slice is high temperature annealed to diffuse the arsenic into the substrate, and then an arsenic doped epitaxial layer is grown on the slice. As recited in the patent, "The slice is then subjected to a boron "deposition" step where the boron is "deposited" in surface areas of the epitaxial layer 12. After the boron glass is removed, the slice is placed in a high temperature furnace tube to diffuse the "deposited" boron through the epitaxial layer 12 until it reaches the silicon substrate 10." Subsequently, several boron layers are deposited sequentially on the epitaxial layer and phosphorous is later diffused into the slice.
U.S. Pat. No. 4,325,180, issued to Curran, relates to a P-JFET based on a monocrystalline p-type silicon substrate with a silicon oxide layer formed thereon. Boron ions are implanted and phosphorous is subsequently applied. After implantation of P-JFET channels, the entire slice receives a boron implant.
U.S. Pat. No. 4,373,253, issued to Khadder, et al., describes a JFET device fabricated into a conventional CMOS monolithic IC to provide linear circuit operation said to have low noise characteristics. The starting substrate is a silicon wafer with a surface oxide. First and second layers of fast diffusing boron implants are added, and a JFET channel is created. Arsenic ions are implanted through a hole in the oxide layer. Channel stops, p-channel source/drain electrodes and JFET gate contacts are created. Phosphorous can be implanted to create an N-type top cap. The noise normally associated with field effect devices is said to be greatly reduced, because all of the JFET active region, the channel, is subsurface.
U.S. Pat. No. 4,496,963, issued to Dunkley, et al., relates to a JFET with a gate region, source/drain regions, and a channel region extending through the gate region between the source and drain regions. For surface stabilization, the channel region has a shallow ion implanted layer of doping material. The substrate is silicon with an oxide layer onto which boron is implanted. Phosphorous is implanted using a very shallow N-type ion implant. In accordance with the disclosure, an N-type ion implant, such as a phosphorous ion implant, is said to stabilize the surface region and eliminate the noise typically generated in JFETS.
U.S. Pat. No. 4,596,068, issued to Peters, describes JFETS in which the surface of the channel and top gates are compensated after a high temperature processing by ion implanting boron onto a silicon substrate through a protective layer. The surface is covered with a thick field oxide. An N-JFET protective layer is grown over the silicon surface. An N-type dopant, such as phosphorous, is then implanted to complete the N-channel of the N-JFET by forming a thin N-channel region displaced below the wafer surface.
U.S. Pat. No. 4,668,971, issued to Hynecek, concerns low noise amplifiers integrated with a CCD array. The gate of the JFET can be formed with the same implant which forms the virtual phase electrode in an array of virtual phase CCD cells. A p-type substrate has an oxide grown on it. A channel stop implant mask is used to expose channel stop regions to a p-type boron implant. A virtual well implant and a blanket virtual barrier implant, both of phosphorous, are then applied. A deep p-type implant of boron is added. To create the buried channel MOSFETs, the moat region in the periphery is exposed to the buried channel implant and a light dose phosphorous implant, which is performed before the poly gate level is patterned. The JFETS of Hynecek are long high-pinchoff devices said to be useful for loads where special low noise performance is required. The JFETS may be used as loads in source-follower stages
U.S. Pat. No. 4,796,073, issued to Bledsoe, relates to improving noise considerations in P channel JFETS. A gettering region is formed in the top surface by producing high concentration surface damage in the semiconductor crystal lattice in the top surfaces. A large inactive N+ region is provided in the P channel JFET to getter impurities away from active areas. The ratio of inactive N+ area to the total area of the transistor is said to be selected to provide suitably low noise measurements at low frequencies.
U.S. Pat. Nos. 4,983,536 and 5,126,805, issued to Bulat, et al., relate to static induction transistor JFETS. Prior to metallization, a thin layer of germanium is intermixed with the underlying silicon and recrystallized to form a germanium-silicon composite. The composite overlies the exposed silicon of the source and gate regions. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Ohmic source and gate contact members are then produced by conventional metallization procedures. The contact resistance of the device is said to be reduced by virtue of the reduced bandgap provided by the presence of the germanium.
JFET technology is presently preferred for cryogenic detectors. The limits of other transistor technologies, including bipolar, silicon-metal oxide semiconductor field effect transistor (Si-MOSFET) and germanium arsenide-metal gate Schottky field effect transistor (GaAs-MESFET) technology, makes them much less compatible for cryogenic applications. For example, the base current of bipolar transistors adds parallel noise to the system degrading its resolution. Si-MOSFETS suffer from radiation damage. Furthermore, Si-MOSFETS are susceptible to generation and recombination effects due to the Si/SiO.sub.2 interface. Typical MESFETS, including GaAs-MESFETS, suffer from excessive power dissipation and are susceptible to interface effects due to the Schottky barrier and the passivation layer interface.
JFETS similar to types described and known in the prior art remain noisy particularly for cryogenic applications. Thus there exists a need for a JFET structure which exhibits low noise characteristic and is simple to manufacture.